? semiconductor components industries, llc, 2013 july, 2013 ? rev. 0 1 publication order number: ncp51510/d ncp51510 3 amp v tt termination source / sink regulator for ddr, ddr-2, ddr-3, ddr-4 the ncp51510 is a source/sink double data rate (ddr) termination regulator specifically designed for low input voltage and low ? noise systems where space is a key consideration. the ncp51510 maintains a fast transient response and only requires a minimum v tt load capacitance of 10 f for output stability. the ncp51510 supports remote sensing and all power requirements for ddr v tt bus termination. the ncp51510 can also be used in low ? power chipsets and graphics processor cores that require dynamically adjustable output voltages. the ncp51510 is available in the thermally ? efficient dfn10 exposed pad package, and is rated both green and pb ? free. features ? generate ddr memory termination voltage (v tt ) ? for ddr, ddr ? 2, ddr ? 3 and ddr ? 4 source / sink currents ? supports loads up to 3 a (typ), output is over ? current protected ? integrated mosfets with thermal shutdown protection ? fast load ? transient response ? p good output pin to monitor status of v tt output regulation ? ss input pin for suspend shutdown mode ? v ri input reference for flexible voltage tracking ? v tts input for remote sensing (kelvin connection) ? built ? in soft start, under voltage lockout ? small, low ? profile 10 ? pin, 3 x 3 mm dfn package ? this is a pb ? free device applications ? ddr memory termination ? desktop pc?s, notebooks, and workstations ? servers and networking equipment ? telecom/datacom, gsm base station ? graphics processor core supplies ? set top boxes, lcd ? tv/pdp ? tv, copier/printers ? supplies power for chipset/ram as low as 0.5 v ? active source/sink bus termination http://onsemi.com device package shipping ? ordering information NCP51510MNTWG dfn10 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. dfn10 case 485c marking diagram pin connections ss xxxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package xxxxx xxxxx alyw (*note: microdot may be in either location) 1 2 3 4 5 10 9 8 7 6 (top view) v ro v cc a gnd v ri p good pv cc v tt p gnd v tts gnd
ncp51510 http://onsemi.com 2 pin function description pin number pin name pin function 1 v ro output ? buffered output of v ri reference input pin. 2 v cc input ? regulator analog power input pin. connect to the system supply voltage. bypass v cc to a gnd with a 1 f or greater ceramic capacitor. 3 a gnd analog ground 4 v ri input ? external reference input for v tt output (see figure 1 for typical application) 5 p good output ? v tt ?power good? pin (open drain output) 6 v tts input ? remote sense input for v tt . the v tts pin provides accurate remote feedback sensing of the v tt output. 7 ss input ? suspend shutdown control input. cmos compatible. logic high = enable, logic low = shutdown. connect to vddq for normal operation. 8 p gnd power ground. internally connected to low ? side mosfet 9 v tt output ? regulated power output pin 10 pv cc input ? regulator power input pin. internally connected to high ? side mosfet ? thermal pad pad for thermal connection. the exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. absolute maximum ratings rating symbol value unit pv cc to p gnd (note 1) ? ? 0.3 to 4.3 v v cc to a gnd (note 1) v cc ? 0.3 to 4.3 v ri , v ro , ss , p good to a gnd (note 1) ? ? 0.3 to (v cc + 0.3) v tt to p gnd (note 1) ? ? 0.3 to (pv cc + 0.3) v tts to a gnd (note 1) v tts ? 0.3 to (pv cc + 0.3) p gnd to a gnd p gnd ? 0.3 to +0.3 storage temperature t stg ? 65 to 150 c operating junction temperature range t j ? 40 to 125 esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v v tt output continuous rms current 100 sec ? 1.6 a 1 sec 2.5 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latchup current maximum rating tested per jedec standard: jesd78. dissipation ratings package t a =70 c power rate derating factor above t a = 70 c 10 ? pin dfn 1951 mw 24.4 mw / c
ncp51510 http://onsemi.com 3 recommened operating conditions rating symbol value unit v tt output voltage range v tt , v tts 0.5 to 1.5 v pv cc input voltage range (power) pv cc 1.1 to 3.6 v cc input voltage range (analog) v cc 2.7 to 3.6 logic voltage range ss , p good 0 to v cc operating ambient temperature range t a ? 40 to +125 c electrical characteristics pv cc = 1.8 v; v cc = 3.3 v; v ri = v tts = 1.25 v; ss = v cc ; (circuit of figure 1, ? 40 c (t j = t a ) 125 c; unless otherwise noted. typical values are at t a = +25 c parameter conditions symbol min typ max unit output v tt output voltage range pv cc > (v tt + v dropout ) v tt 0.5 1.5 v v tt load regulation ? 1 a i tt +1 a v load ? 4 +4 mv v tt line ? regulation 1.4 v pv cc 3.3 v, i out = 100 ma v line 1 feedback ? voltage error v ri to v tts , i tt = 200 ma t a = ? 40 c to 125 c v tts ? 17 +17 v tt current slew rate c out = 100 f, i tt = 0.1 a to 2 a i tt di/dt 3 a/ s v tt output power ? supply rejec- tion ratio 10 hz < f < 10 khz, i tt = 200 ma, c out = 100 f psrr 80 db v tt output mosfet r ds(on) high ? side (source) (i tt = +100 ma) r ds(on) 140 250 m low ? side (sink) (i tt = ? 100 ma) 140 250 v tt output ? to ? v tts input internal feedback resistance r fb 12 k discharge mosfet r ds(on) ss = 0 v r dis 8 supply current quiescent pv cc current no load i pvcc 0.4 10 ma quiescent v cc current v ri > 0.45 v, no load i cc 0.7 1.3 shutdown pv cc current ss = 0 v i pvcc sd 0.1 10 a shutdown v cc current ss = 0v, v ri = 0 v i cc sd 50 100 ss = 0v, v ri > 0.45 v 350 600 reference v ri input voltage range v ri 0.5 1.5 v v ri input ? bias current t a = +25 c i ri ? 1 +1 a v ro output voltage v cc = 3.3 v, i ro = 0 v ro v ri ? 10 v ri v ri +10 mv v ro load regulation i ro = 5 ma v ro ? 20 +20 suspend shutdown ss ? suspend shutdown logic input threshold ss logic hi (v tt output enabled) v ih 2.0 v ss logic low (v tt suspended) v il 0.8 ss ? logic input current ss = v cc or 0 v, t a = +25 c i ss ? 1 +1 a fault condition ? current limit current ? limit threshold t a = ? 40 c to +125 c i tt limit 1.8 3 4.2 a soft ? start current ? limit time t ss 200 s
ncp51510 http://onsemi.com 4 electrical characteristics pv cc = 1.8 v; v cc = 3.3 v; v ri = v tts = 1.25 v; ss = v cc ; (circuit of figure 1, ? 40 c (t j = t a ) 125 c; unless otherwise noted. typical values are at t a = +25 c (continued) parameter unit max typ min symbol conditions fault condition ? under ? voltage lockout v cc uvlo threshold wake ? up, rising edge v cc uvlo 2.50 2.70 2.90 v hysteresis voltage ? 100 mv pv cc uvlo threshold wake ? up, rising edge pv cc uvlo 0.9 1.1 v hysteresis voltage ? 55 mv v ri uvlo voltage v ri , rising edge v ri uvlo 350 450 hysteresis voltage ? 50 fault condition ? thermal shutdown thermal shutdown temperature thermal shutdown, rising edge t sd 165 c thermal shutdown hysteresis hysteresis temperature t sh 15 fault condition ? power good p good lower trip threshold with respect to feedback threshold, hysteresis = 12 mv ? ? 200 ? 150 ? 100 mv p good upper trip threshold ? 100 150 200 p good output low voltage i sink = 4 ma (p good mosfet = on) ? 300 p good start ? up delay start ? up rising edge, v tts within 100 mv of the feedback threshold ? 1 2 3.5 ms p good propagation delay v tts forced 25 mv beyond p good trip threshold t pgood 5 10 35 s p good leakage current v tts = v ri (p good hi ? impedance), p good = v cc + 0.3 v, t a = +25 c i pgood 1 a
ncp51510 http://onsemi.com 5 general* the ncp51510 is a source/sink tracking termination regulator specifically designed for low input voltage and low external component count systems where space is a key application parameter. the ncp51510 integrates a high ? performance, low ? dropout (ldo) linear regulator that is capable of both sourcing and sinking current. the ldo regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. to achieve tight regulation with minimum effect of trace resistance, a remote sensing input (v tts ) should be connected to the positive terminal of the output capacitors as a separate trace from the high current path of the v tt output. generation of internal voltage reference the v tt output voltage is regulated to (and tracks with) the voltage on the v ri reference input. when the v ri input is configured for standard ddr termination applications, the v ri reference input can be set by an external equivalent ratio voltage divider connected to the memory supply bus (v ddq ). the ncp51510 supports v tt voltages from 0.5 v to 1.5 v. generation of internal voltage reference (cont) when the v ro output is configured for ddr termination applications, it provides a separate v tt output reference voltage for the memory application. the v ro reference o utput pin is a buffered version of the v ri reference input, and is capable of sourcing and sinking a load of 5 ma. the v ro output becomes active when the v ri input > 0.45 v and the v cc power rail is above the uvlo threshold. the v ro reference o utput is independent of the ss pin (suspend shutdown) state. fault detection and shutdown function when the ss ?suspend shutdown? input pin is driven high, the ncp51510 regulator begins normal operation, with the soft start circuit gradually increasing output current during the first 200 s in order to reduce the input surge currents at startup, with full current available after the 200 s soft ? start circuitry has timed out. when the ss input is driven low, the v tt output is discharged to p gnd through an internal 8 mosfet. the v ro output remains on when the ss input is driven low. the ncp51510 provides an open ? drain p good ?power good? output that goes high when the v tts sense input is within 150 mv of the v ri reference input. the p good output de ? asserts within 10 s after the v tts sense input exceeds the size of the p good window. during initial v tt startup, p good asserts high 2 ms after the v tts sense input enters p good window. because the p good output is open ? drain, an external pull ? up resistor is required (100 k *) between p good and a stable active supply voltage rail. thermal shutdown with hysteresis if the ncp51510 is to operate in elevated temperatures for long durations, care should be taken to ensure that the maximum operating junction temperature is not exceeded. to guarantee safe operation, the ncp51510 provides on ? chip thermal shutdown protection. when the chip junction temperature exceeds 165 c*, the part will shutdown. when the junction temperature falls back, to 150 c*, the device resumes normal operation. if the junction temperature exceeds the thermal shutdown threshold, the v tt output is shut of f, discharged by the 8 internal discharge mosfet. output capacitor output stability is guaranteed for v tt output capacitance c out from 10 f to 220 f. the esr of c out between 2 m and 50 m is required to maintain stability. use the formula below to calculate the application?s transient response: i tt(pp) esr v tt(pp) where: i tt(pp) is the maximum peak ? to ? peak load current delta and v tt(pp) is the allowable peak ? to ? peak voltage tolerance. *typical values are used with the application description text. please refer to the electrical specifications table for a more detailed list of min, max and typical values.
ncp51510 http://onsemi.com 6 figure 1. standard application schematic for ncp51510
ncp51510 http://onsemi.com 7 package dimensions dfn10, 3x3, 0.5p case 485c issue c 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. 7. for device opn containing w option, detail b alternate construction is not applicable. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp51510/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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